Fault-Tolerance Techniques for SRAM-Based FPGAs eBook
$39.99
Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers.
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About this eTextbook
Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise.
The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs).
It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described.
Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault tolerant techniques for programmable logic applications.
ISBNs for Fault-Tolerance Techniques for SRAM-Based FPGAs are 9780387310695, 038731069X and the print ISBNs are 9781441940520, 1441940529. Additional ISBNs include 9780387310688.
Publication details
- Author: Fernanda Lima Kastensmidt; Ricardo Reis
- Publisher: Springer
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About this eTextbook
Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise.
The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs).
It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described.
Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault tolerant techniques for programmable logic applications.
ISBNs for Fault-Tolerance Techniques for SRAM-Based FPGAs are 9780387310695, 038731069X and the print ISBNs are 9781441940520, 1441940529. Additional ISBNs include 9780387310688.
Publication details
- Author: Fernanda Lima Kastensmidt; Ricardo Reis
- Publisher: Springer
What you receive
- A licensed digital edition of this title, supplied as PDF or EPUB. The format is set by the publisher, so email us the ISBN before ordering and we will confirm which one it is.
- Delivered to the email address on your order as a secure download link, usually within minutes and always within 24 hours of payment.
- Download links do not expire and there is no cap on re-downloads. Readable on any computer, tablet or phone, online or offline.
- This is a digital edition. Nothing is printed, packed or posted, and there is no delivery charge.
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