Advanced HDL Synthesis and SOC Prototyping: RTL Design Using Verilog eBook
$39.99
This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks.
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About this eTextbook
This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies.
The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike.
Publication details
- Author: Vaibbhav Taraate
- Publisher: Springer
- eText ISBN: 9789811087769, 9811087768
- Print ISBN: 9789811087752, 981108775X
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About this eTextbook
This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies.
The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike.
Publication details
- Author: Vaibbhav Taraate
- Publisher: Springer
- eText ISBN: 9789811087769, 9811087768
- Print ISBN: 9789811087752, 981108775X
What you receive
- A licensed digital edition of this title, supplied as PDF or EPUB. The format is set by the publisher, so email us the ISBN before ordering and we will confirm which one it is.
- Delivered to the email address on your order as a secure download link, usually within minutes and always within 24 hours of payment.
- Download links do not expire and there is no cap on re-downloads. Readable on any computer, tablet or phone, online or offline.
- This is a digital edition. Nothing is printed, packed or posted, and there is no delivery charge.
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