ASIC Design and Synthesis: RTL Design Using Verilog eBook
$39.99
This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog.
Digital edition, delivered to your inbox within 24 hours of payment. No shipping, no delivery charge.
About this eTextbook
This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution.
The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.
Publication details
- Author: Vaibbhav Taraate
- Publisher: Springer
- eText ISBN: 9789813346420, 9813346426
- Print ISBN: 9789813346413, 9813346418
What you receive
- A licensed digital edition of this title, supplied as PDF or EPUB. The format is set by the publisher, so email us the ISBN before ordering and we will confirm which one it is.
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- This is a digital edition. Nothing is printed, packed or posted, and there is no delivery charge.
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About this eTextbook
This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution.
The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.
Publication details
- Author: Vaibbhav Taraate
- Publisher: Springer
- eText ISBN: 9789813346420, 9813346426
- Print ISBN: 9789813346413, 9813346418
What you receive
- A licensed digital edition of this title, supplied as PDF or EPUB. The format is set by the publisher, so email us the ISBN before ordering and we will confirm which one it is.
- Delivered to the email address on your order as a secure download link, usually within minutes and always within 24 hours of payment.
- Download links do not expire and there is no cap on re-downloads. Readable on any computer, tablet or phone, online or offline.
- This is a digital edition. Nothing is printed, packed or posted, and there is no delivery charge.
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